1. Field of the Invention
The present invention relates to a NAND flash memory including a memory cell including control gates on both sides of a floating gate with IPD layers interposed between the control gate and the floating gate respectively, and to a method of manufacturing the same.
2. Discussion of the Background
NAND flash memories have been increasingly miniaturized in recent years. Along with the advancement of the miniaturization, it is difficult for a background memory cell of a laminated polysilicon type to ensure a high coupling ratio because of an effect of parasitic capacitance as expressed by the following formulae (1) to (3).
Here, a correlation among a capacitance Cox, a film thickness tox, and an area Sox of a tunnel oxide film is expressed by the formula (1), in which ε is permittivity.Cox=εSox/tox  (1)
Meanwhile, a correlation among a capacitance Cipd, a capacitance thickness tipd (in terms of SiO2), and an area Sipd, of a dielectric layer between two adjacent polysilicon layers (IPD) is expressed by the formula (2).Cipd=εSipd/tipd  (2)
Therefore, a coupling ratio Cr is expressed by the formula (3).Cr=Cipd/(Cox+Cipd)  (3)
Here, a NAND flash memory having a cell structure in which control gates CG are arranged on both sides of a floating gate FG has been proposed in recent years (see Japanese Patent Application Publication No. 2005-45224, for example). In this NAND flash memory, a side wall of the floating gate can ensure a desired coupling ratio Cr expressed by the formula (3).
In the above-described background NAND flash memory, for example, the floating gate FG is reduced in film thickness as much as possible so that a bottom surface of the control gate CG is vertically aligned with a surface of a silicon substrate as closely as possible. In this way, a parasite capacitance between adjacent cells is reduced while the desired coupling ratio is ensured.
In the above-described background NAND flash memory, the coupling ratio Cr needs to be increased in order to achieve a wide range of threshold voltages, for example with the application of a high writing voltage Vpgm or with the reduction of the parasite capacitance between adjacent cells. In this case, a problem arises in that an electric short-circuit may occur between the control gate CG and the semiconductor (silicon) substrate (as described in Japanese Patent Application Publication No. 2005-45224, for example).